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1. general description the ptn3700 is a 1.8 v simple mobile interfac e link bridge ic which can function both as a transmitter-serializer or a receiver-deserializer for rgb888 video data. when configured as transmitter (using input pin tx/rx ), the ptn3700 serializes parallel cmos video input data into 1, 2 or 3 sublvds-based high-speed serial data channels. when configured as receiver, the ptn3700 deserializes up to 3 high- speed serial data channels into parallel cmos video data signals. the parallel interface of the ptn3700 is based on the conventional and widely used 24-bit wide data bus for rgb video data, plus active low hs (horizontal synchronization) and vs (vertical synchronization) signals, and an active high de (data enable) signal. an additional two auxiliary bits a[ 1:0] are provided to permit si gnaling of misce llaneous status or mode information across the link to the disp lay. the serial interface link of the ptn3700 is based on the open simple mobile interfac e link (smili) definition. in order to keep power low while accommodating various display sizes (e.g., up to 24-bit, 60 frames per second xvga), the number of high-speed seri al channels (?lanes?) is configurable from 1 to 3 depending on the bandwidth needed. the data link speed is determined by the pclk (pixel clock) rate and the number of serial channels selected. in order to maintain a low power profile, the ptn3700 has three power modes, determined by detection of an active input clock and by shutdown pin xsd . in shutdown mode (xsd = low), the ptn3700 is completely in active and consumes a minimum of current. in standby mode (xsd = high), the device is ready to switch to active mode as soon as an active input clock signal is detected, and assume normal link operation. in transmitter mode, the ptn3700 performs parity calculation on the input data (r[7:0], g[7:0], b[7:0] plus hs , vs and de data bits) and adds an odd parity bit cp to the serial transmitted data stream. the ptn3700 in re ceiver mode also integrates a parity checking function, which checks for odd pari ty across the decoded input word (r[7:0], g[7:0], b[7:0] plus hs , vs and de data bits), and indicates whether a parity error has occurred on its cpo out pin (active high). when a parity error occurs, the most recent error-free pixel data will be output instead of the received invalid pixel data. ptn3700 in receiver mode offers an opti onal advanced frame mixing feature, which allows 18-bit displays to ef fectively display 24-bit color resolution by applying a patent-pending pixel data processing algorithm to the 24-bit video input data. one of two serial transmissi on methods is selectable: pseudo source synchronous transmission based on the pixel clock, or true source synchronous transmission based on the bit clock. the latter uses a patent-pending methodology characterized by zero overhead and operation guaranteed fr ee from false pixel synchronization. ptn3700 1.8 v simple mobile interface link bridge ic rev. 2 ? 8 june 2011 product data sheet
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 2 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic the ptn3700 automatically rotates the order of the essential signals (parallel cmos and high-speed serial data and clock) depending on whether it is operating as transmitter or as receiver (using pin tx/rx ). in addition, two pinning select bits (inputs psel[1:0]) allow for four additional signal order configurations. th is allows for various topologies of printed circuit board or flex foil la yout without crossing of traces, and enables the easy introduction of ptn3700 into an existing ?parallel? design avoiding board re-layout. the ptn3700 is available in a 56-ball vfbga package and operates across a temperature range of ? 40 ? c to +85 ? c. 2. features and benefits ? configurable as either transmitter or receiver ? one of two serial transmission methods selectable (pixel clock referenced pseudo source synchronous or bit clock referenced true source synchronous) ? 3 differential sublvds high-speed serial lanes ? one differential pixel clock ? configurable aggregate data bandwidth allowing up to 24-bit color, 60 fps xga: ? 1 lane at 30 ? serialization rate up to 650 mbit/s ? 2 lanes at 15 ? serialization rate up to 1300 mbit/s ? 3 lanes at 10 ? serialization rate up to 1.95 gbit/s ? parity encoding (transmitter) and detection (receiver) with last valid pixel repetition ? advanced frame mixing function (in receiv er mode) for 24-bit color depth using conventional 18-bit displays or specially adapted ?18-bit plus? displays ? parallel cmos i/o based on interface definition of rgb888 plus hs , vs , de ? very low power profile: ? shutdown mode for minimum idle power (< 3 ? a typical) ? low-power standby mode with input clock frequency auto-detect (< 3 ? a typical) ? low active transmitter powe r: 18 mw (typ.) for qvga 1 and 40 mw (typ.) for wvga 2 ? low active receiver power: 15 mw (typ .) for qvga and 36 mw (typ.) for wvga ? slew rate control on receiver parallel cmos outputs ? operates from a single 1.8 v ? 150 mv power supply ? configurable mirroring pinout (dependent on tx or rx mode and psel[1:0] inputs) for optimum single layer flex-foil flow-through in various application scenarios ? available in 56-ball vfbga package 3. applications ? high-resolution mobile phones ? portable applications wit h video display capability 1. qvga: 240 ? 320 pixels at 60 hz frame rate; 20 % non-active displa y data overhead; pclk at 5.5 mhz; one-lane operation at 166 mbit/s; 24-bit color data. 2. wvga: 854 ? 480 pixels at 60 hz frame rate; 20 % non-active display data overhead; pclk at 29.5 mhz; two-lane operation at 885.4 mbit/s; 24-bit color data.
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 3 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 4. ordering information [1] 0.5 mm ball pitch; 1.0 mm maximum package height. 4.1 ordering options 5. functional diagram table 1. ordering information type number solder process package name description version ptn3700ev/g pb-free (snagcu solder ball compound) vfbga56 plastic very thin fine-pitch ball grid array package; 56 balls; body 4 ? 4.5 ? 0.65 mm [1] sot991-1 table 2. ordering options type number topside mark temperature range ptn3700ev/g 3700 ? 40 ? c to +85 ? c fig 1. functional diagram of ptn3700 in transmitter mode ptn3700 d0+ serializer d0 ? d1+ d1 ? d2+ d2 ? vdd vdda protocol mapping, parity encoding, sync word encoding input register 8 r[7:0] 8 g[7:0] 8 b[7:0] 2 a[1:0] hs vs de 1 0 2 clk+ clk ? pll pclk n pclk 1 pclk fss configuration and power management 002aab363 2 ls[1:0] 2 psel[1:0] xsd fss tx/rx = high gnd gnda
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 4 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic fig 2. functional diagram of ptn3700 in receiver mode ptn3700 d0+ output register d0 ? d1+ d1 ? d2+ d2 ? vdd vdda protocol parsing, parity detection, advanced frame mixing, sync word decoding deserializer 8 r[7:0] 8 g[7:0] 8 b[7:0] 2 a[1:0] hs vs de 0 1 clk+ clk ? pll pclk n pclk fss configuration and power management 002aab364 2 ls[1:0] 2 psel[1:0] xsd fss tx/rx = low gnd gnda f/xs fm ddr sdr cpo
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 5 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 6. pinning information 6.1 pinning fig 3. ball configuration for vfbga56 002aac377 ptn3700ev/g transparent top view ball a1 index area a 1234567 b c d e f g h 56-ball, 7 ? 8 grid; transparent top view 56-ball, 7 ? 8 grid; transparent top view fig 4. vfbga56 ball mapping - transmitter mode (tx/rx = high); psel[1:0] = 00b fig 5. vfbga56 ball mapping - transmitter mode (tx/rx = high); psel[1:0] = 01b 56-ball, 7 ? 8 grid; transparent top view 56-ball, 7 ? 8 grid; transparent top view fig 6. vfbga56 ball mapping - transmitter mode (tx/rx = high); psel[1:0] = 10b fig 7. vfbga56 ball mapping - transmitter mode (tx/rx = high); psel[1:0] = 11b d2+ vdda de hs b0 b2 123456 d2 ? gnda vs pclk b1 b3 a b d1+ tx/rx a1 gnd vdd b6 c d1 ? psel0 ls0 fm g0 d clk+ gnd psel1 ls1 fss g2 e clk ? f/xs gnd vdd g4 f vdd a0 b4 7 b5 b7 g1 g3 g5 d0+ xsd r6 r4 r2 r0 g d0 ? cpo r5 r3 r1 hr7 g6 g7 002aac378 d2+ vdda de hs r7 r5 123456 d2 ? gnda vs pclk r6 r4 a b d1+ tx/rx a1 gnd vdd r1 c d1 ? psel0 ls0 fm g7 d clk+ gnd psel1 ls1 fss g5 e clk ? f/xs gnd vdd g3 f vdd a0 r3 7 r2 r0 g6 g4 g2 d0+ xsd b1 b3 b5 b7 g d0 ? cpo b2 b4 b6 hb0 g1 g0 002aac379 d0 ? vdda de hs b0 b2 123456 d0+ gnda vs pclk b1 b3 a b clk ? tx/rx a1 gnd vdd b6 c clk+ psel0 ls0 fm g0 d d1 ? gnd psel1 ls1 fss g2 e d1+ f/xs gnd vdd g4 f vdd a0 b4 7 b5 b7 g1 g3 g5 d2 ? xsd r6 r4 r2 r0 g d2+ cpo r5 r3 r1 hr7 g6 g7 002aac380 d0 ? vdda de hs r7 r5 123456 d0+ gnda vs pclk r6 r4 a b clk ? tx/rx a1 gnd vdd r1 c clk+ psel0 ls0 fm g7 d d1 ? gnd psel1 ls1 fss g5 e d1+ f/xs gnd vdd g3 f vdd a0 r3 7 r2 r0 g6 g4 g2 d2 ? xsd b1 b3 b5 b7 g d2+ cpo b2 b4 b6 hb0 g1 g0 002aac381
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 6 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 56-ball, 7 ? 8 grid; transparent top view 56-ball, 7 ? 8 grid; transparent top view fig 8. vfbga56 ball mapping - receiver mode (tx/rx = low); psel[1:0] = 00b fig 9. vfbga56 ball mapping - receiver mode (tx/rx = low); psel[1:0] = 01b 56-ball, 7 ? 8 grid; transparent top view 56-ball, 7 ? 8 grid; transparent top view fig 10. vfbga56 ball mapping - receiver mode (tx/rx = low); psel[1:0] = 10b fig 11. vfbga56 ball mapping - receiver mode (tx/rx = low); psel[1:0] = 11b d2+ vdda r7 r5 r3 r1 123456 d2 ? gnda r6 r4 r2 r0 a b d1+ tx/rx a1 gnd vdd g5 c d1 ? psel0 ls0 fm g3 d clk+ gnd psel1 ls1 fss g1 e clk ? f/xs gnd vdd b7 f vdd a0 g7 7 g6 g4 g2 g0 b6 d0+ xsd pclk b1 b3 g d0 ? cpo b0 b2 hde b5 b4 002aac382 vs hs d2+ vdda b0 b2 b4 b6 123456 d2 ? gnda b1 b3 b5 b7 a b d1+ tx/rx a1 gnd vdd g2 c d1 ? psel0 ls0 fm g4 d clk+ gnd psel1 ls1 fss g6 e clk ? f/xs gnd vdd r0 f vdd a0 g0 7 g1 g3 g5 g7 r1 d0+ xsd pclk r6 r4 g d0 ? cpo r7 r5 hde r2 r3 002aac383 vs hs d0 ? vdda r7 r5 r3 r1 123456 d0+ gnda r6 r4 r2 r0 a b clk ? tx/rx a1 gnd vdd g5 c clk+ psel0 ls0 fm g3 d d1 ? gnd psel1 ls1 fss g1 e d1+ f/xs gnd vdd b7 f vdd a0 g7 7 g6 g4 g2 g0 b6 d2 ? xsd pclk b1 b3 g d2+ cpo b0 b2 hde b5 b4 002aac384 vs hs d0 ? vdda b0 b2 b4 b6 123456 d0+ gnda b1 b3 b5 b7 a b clk ? tx/rx a1 gnd vdd g2 c clk+ psel0 ls0 fm g4 d d1 ? gnd psel1 ls1 fss g6 e d1+ f/xs gnd vdd r0 f vdd a0 g0 7 g1 g3 g5 g7 r1 d2 ? xsd pclk r6 r4 g d2+ cpo r7 r5 hde r2 r3 002aac385 vs hs
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 7 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 6.2 pin description [1] depends on configuration. table 3. pin description - transmitter mode symbol pin [1] type description parallel data inputs r[7:0], g[7:0], b[7:0] cmos 8-bit wide r, g, b pixel data inputs hs cmos horizontal synchronization data input, active low vs cmos vertical synchronization data input, active low de cmos data enable input, active high a0, a1 cmos auxiliary input bits high-speed serial outputs d0+, d0 ? , d1+, d1 ? , d2+, d2 ? sublvds driver serialized high-speed differential sublvds data outputs clk+, clk ? sublvds driver serialized high-speed differential sublvds clock outputs clock inputs pclk cmos pixel clock reference input configuration inputs tx/rx cmos transmitter/receiver configurati on input pin. when high, ptn3700 is configured as transmitter. ls0, ls1 cmos serialization mode program pins. select between 1, 2 or 3 lanes. see ta b l e 5 . psel0, psel1 cmos pin mirror ing select pins. see ta b l e 6 and ta b l e 7 xsd cmos shutdown mode input pin, active low, puts ptn3700 in lowest-power mode by deactivating all circuitry. when high, ptn3700 is either in active mode or awaiting clock input (standby mode) fss cmos fully source synchronous select pin. when low, ptn3700 uses pseudo source synchronous serial transmission mode with the pixel clock as both the reference frequency and the fram e boundary delineation. when high, ptn3700 uses true source synchronous transmission with a serial double data rate (ddr) bit clock for the serial data. embedded synchronization words are encoded for pixel synchronization. on both receiver and transmitter, the settings of the fss pin should match. otherwise the link will not function. power supply vdd power power supply voltage vdda power analog (pll) power supply voltage gnda ground analog (pll) ground gnd ground ground miscellaneous cpo, fm, f/xs cmos signals are inactive in transmitter mode and should be tied down to gnd.
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 8 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic [1] depends on configuration. table 4. pin description - receiver mode symbol pin [1] type description parallel data outputs r[7:0], g[7:0], b[7:0] cmos 8-bit wide r, g, b pixel data outputs hs cmos horizontal synchronization data output, active low vs cmos vertical synchronization data output, active low de cmos data enable output, active high a0, a1 cmos auxiliary output bits high-speed serial inputs d0+, d0 ? , d1+, d1 ? , d2+, d2 ? sublvds receiver serialized high-speed differential sublvds data inputs clk+, clk ? sublvds receiver serialized high-speed differential sublvds clock inputs clock outputs pclk cmos pixel clock output configuration inputs tx/rx cmos transmitter/receiver configuration input pin. when low, ptn3700 is configured as receiver. ls0, ls1 cmos serialization mode program pi ns. select between 1, 2 or 3 lanes. see ta b l e 5 . psel0, psel1 cmos pin mirrori ng select pins. see ta b l e 6 and ta b l e 7 . xsd cmos shutdown mode input pin, active low, puts ptn3700 in lowest-power mode by deactivating all circuitry. when high, ptn3700 is either in active mode or awaiting clock input (standby mode). f/xs cmos program pin for fast (f/xs = high) or slow (f/xs = low) parallel output and pclk slew rate fm cmos frame mixing select pin. when low, frame mixing is disabled and ptn3700 passes 24-bit video data transparently. when high, frame mixing is enabled and ptn3700 applies processing to the 24-bit video data resulting in 18-bit output data words encoded with 24-bit color depth. frame mixing is only available in receiver mode. fss cmos fully source synchronous select pin. when low, ptn3700 uses pseudo source synchronous serial reception mode with the pixel clock as both the reference frequency and the frame boundary delineation. when high, ptn3700 uses true source synchronous reception with embedded synchronization word decoding, with the bit clock as reference frequency. on both receiver and transmitter, the settings of the fss pin should match. otherwise the link will not function. parity output cpo cmos parity error output, active high. a high level indicates a parity error was detected in the current pixel data power supply vdd power supply voltage vdda analog (pll) power supply voltage gnda analog (pll) ground gnd ground
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 9 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7. functional description 7.1 general a complete simple mobile interface link consists of one ptn3700 configured as transmitter (see figure 1 ); two, three or four differ ential-pair high-speed signaling channels; and one ptn3700 configured as receiver (see figure 2 ). link power and ground are supplied to pins vdd and gnd re spectively (power and ground should be routed and decoupled to analog supply pin vdda and ground pin gnda separately for lowest jitter operation). configuration of either transmitter or receiver mode is achieved by strapping the cmos input pin tx/rx high or low, respectively. configured as transmitter, ptn3700 accepts parallel cmos input da ta including color pixel data (r[7:0], g[7:0], b[ 7:0]), three control bits hs (horizontal synchronization), vs (vertical synchronization), de (data enable), auxiliary bits a[1:0] and pixel clock pclk. the ptn3700 calculates a parity bi t (excluding the auxiliary bits, see section 7.6 ) and serializes the data and outputs as a high-speed serial data stream on up to three sublvds differential outputs (d0+, d0 ? , d1+, d1 ? , d2+, d2 ? ) depending on the serialization mode selected by pins ls[1:0] (see section 7.2 ). an integrated low-jitter pll generates internally the bit clock used for serialization of video input data, parity bit and control bits, and outputs along with the seri al output data a differential pixel clock on differential sublvds output pair clk+ and clk ? . configured as receiver, ptn3700 accepts serial differential data inputs d0+, d0 ? , d1+, d1 ? , d2+, d2 ? and differential input clock clk+ and clk ? from the signaling channel and deserializes the received data into parallel output data on pins r[7:0], g[7:0], b[7:0], hs , vs , de and a[1:0] along with the pll-regener ated pixel clock pclk. also, a parity checking function is performed on th e incoming r[7:0], g[7:0], b[7:0], hs , vs , de bits and an error flagged by signaling a high state on cmos output pin cpo (see section 7.6 ). serialization mode pins ls[1:0] need to be selected according to the expected serialization mode (see section 7.2 ) to correctly receive and decode the up to three sublvds differential serial inputs. to minimize emi, the parallel outputs can be configured by tying pin f/xs either high or low to output fast or slow output slew rates respectively. the ptn3700 is capable of operating in either of two distinct transmission modes: pseudo source synchronous mode (pss) , and full (or ?true? ) source synchron ous mode (fss), selected by cmos input pin fss. in pss mode, the pixel clock pclk is used both as the transmission frequency reference and its rising edge as the delineation of the start of a pixel. this transmission mode relies on the receiver pll to reconstruct the bit clock at the receiving end. in fss mode, the bit clock is transmitted (in ddr mode) instead of the pixel clock. rather than ac hieve frame boundary de tection using the pixe l clock edge as in pss mode, in fss mode the transmitter encodes ?synchronization words? over the link which are detected and used for data to pixel alignment by the receiver. this methodology guarantees false-synchronization-free transmission with zero protocol overhead. the ptn3700 can be put into very low ?shut down? power state by tying cmos input pin xsd low. additionally, the pt n3700 will automatically enter a low-power ?standby? mode when no active input clock is detected on its inputs (see section 7.5 ).
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 10 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7.2 link programmability the number of high-speed serial channels used is programmed by cmos input pins ls[1:0]. for a given link consisting of a transm itter and receiver pair of ptn3700?s, the number of channels us ed must be programmed identically or the link will malfunction. the ptn3700, once programmed, w ill assume the corresponding se rialization ratio as shown in ta b l e 5 . when pins ls[1:0] are both high, the ptn3700 is put in a test mode which is used for production testing purposes only and should not be used in application. the 1-lane mode is typically meant for sma ller video display formats (e.g., qvga to hvga), while the 2-lane mode is typically us ed for display formats like hvga and vga. the 3-lane mode supports larger display formats such as vga or xga. please see section 12.1 for more information. [1] mode 11 is used for test purposes only. 7.3 versatile signal mirroring programmability in order to provide flexibility for different sig nal order and flow requ irements in different applications, the ptn3700 can be programmed to mirror its signal order for the parallel and serial i/os indepe ndently using the psel[1 :0] inputs. the signal order also changes as a function of the tx/rx input by mirroring signals in such a way that the transmitter and receiver in a given link can be connec ted without signal crossings by simply opposing the two instances of ptn3700 and rotating one of them by 180 degrees. the truth table for the versatile signal mirroring scheme is shown in table 6 and ta b l e 7 . the individual ball mappings are given in figure 4 through figure 11 . table 5. link programmability ls1 ls0 mode number of high-speed serial channels supported pclk frequency range (mhz) guaranteed data bandwidth per channel (mbit/s) guaranteed aggregate link bandwidth (mbit/s) l l 00 1 4.0 to 21.6 120 to 650 650 l h 01 2 8.0 to 43.3 120 to 650 1300 h l 10 3 20.0 to 65.0 200 to 650 1950 h h 11 reserved [1] reserved reserved reserved
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 11 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic [1] for ptn3700ev/g vfbga56 package option. see also figure 4 through figure 11 . table 6. versatile signal mirroring programmability - parallel i/o ball location [1] tx/rx l h psel0 l h l h (receive mode) (transmit mode) h3 de de r7 b0 g3 vs vs r6 b1 h4 hs hs r5 b2 g4 pclk pclk r4 b3 h5 b0 r7 r3 b4 g5 b1 r6 r2 b5 h6 b2 r5 r1 b6 g6 b3 r4 r0 b7 h7 b4 r3 g7 g0 g7 b5 r2 g6 g1 f7 b6 r1 g5 g2 f6 b7 r0 g4 g3 e7 g0 g7 g3 g4 e6 g1 g6 g2 g5 d7 g2 g5 g1 g6 d6 g3 g4 g0 g7 c7 g4 g3 b7 r0 c6 g5 g2 b6 r1 b7 g6 g1 b5 r2 a7 g7 g0 b4 r3 b6 r0 b7 b3 r4 a6 r1 b6 b2 r5 b5 r2 b5 b1 r6 a5 r3 b4 b0 r7 b4 r4 b3 pclk pclk a4 r5 b2 hs hs b3 r6 b1 vs vs a3 r7 b0 de de
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 12 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic [1] for ptn3700ev/g vfbga56 package option. see also figure 4 through figure 11 . 7.4 high-speed data channel protocol options the ptn3700 maps the transmission protocol in accordance with the serialization mode selected by pins ls[1:0]. in mode 00 (1-cha nnel), all rgb, parity and synchronization bits are serialized onto a single 30-bit sequence. in mode 01 (2-channel), these bits are mapped onto two simultaneous 15-bit sequences divided across two lanes. in mode 10 (3-channel), the 30 bits are serialized onto three simultaneous 10-bit sequences. the serial bit mapping is different between pseudo-source-synchronous mode (fss = low) and fully source-synchronous mode (fss = high). the mapping of the data bits in pseudo-source synchronous mode is shown in figure 12 , figure 13 and figure 14 . (note that the clk in mode 01 has an as ymmetrical duty cycle of 8/15). the serial bit mapping in fully source-synchronous mode is shown in figure 15 , figure 16 and figure 17 . note that the fully source synchronous transmission mode is not dependent on the phase of pclk for receiver synchronization. table 7. versatile signal mirror ing programmability - serial i/o ball location [1] psel1 l h a1 d2+ d0 ? b1 d2 ? d0+ c1 d1+ clk- d1 d1 ? clk+ e1 clk+ d1 ? f1 clk ? d1+ g1 d0+ d2 ? h1 d0 ? d2+
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 13 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7.4.1 serial protocol bit mapping - pseudo source synchronous mode (fss = low) fig 12. mode 00 - single serial data channel mode (fss = low) 002aac862 r7 r6 r1 r0 g7 g6 g1 g0 b7 b6 b1 b0 vs hs a1 a0 de r7 cp d0 (differential) clk (differential) 1 / f o(pclk) or 1 / f i(pclk) fig 13. mode 01 - dual serial data channel mode (fss = low) 002aac863 g3 g2 g0 b7 b6 b5 b3 b2 b1 b0 de a1 g3 g2 d1 (differential) clk (differential) g1 b4 hs r7 r6 r4 r3 r2 r1 g7 g6 g5 g4 a0 cp r7 r6 d0 (differential) r5 r0 vs 1 / f o(pclk) or 1 / f i(pclk) fig 14. mode 10 - triple serial data channel mode (fss = low) 002aac864 b7 b6 b4 b3 b2 b1 de a1 b7 b6 d2 (differential) clk (differential) b5 b0 g7 g6 g4 g3 g2 g1 a0 g7 g6 d1 (differential) g5 g0 r7 r6 r4 r3 r2 r1 cp r7 r6 d0 (differential) r5 r0 vs hs 1 / f o(pclk) or 1 / f i(pclk)
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 14 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7.4.2 serial protocol bit mapping - fully source synchronous mode (fss = high) fig 15. mode 00 - single serial data channel mode (fss = high) 002aac871 de hs r0 b0 d0 (differential) clk (differential) vs g7 g0 r7 r1 g1 b5 a1 b6 a0 cp b7 de b1 1 / f o(pclk) or 1 / f i(pclk) fig 16. mode 01 - dual serial data channel mode (fss = high) fig 17. mode 10 - triple serial data channel mode (fss = high) 002aac872 g4 g5 g7 a1 d1 (differential) clk (differential) g6 a0 b3 b2 b0 b4 cp g4 b6 de hs r0 g0 d0 (differential) vs r7 r4 r3 r1 r5 g3 g1 r2 r6 g2 de b1 b5 b7 1 / f o(pclk) or 1 / f i(pclk) 002aac873 b1 b2 b4 d2 (differential) clk (differential) b3 b6 a1 b5 b7 b1 r7 g0 g2 d1 (differential) g1 g6 g5 g3 g7 g4 b0 r7 a0 cp de hs r0 d0 (differential) vs r4 r3 r1 r5 r2 r6 de 1 / f o(pclk) or 1 / f i(pclk)
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 15 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7.4.3 pll, pclk, clk and pixel synchronization 7.4.3.1 pixel synchronization pss mode: the serial clock clk provides the word boundaries explicitly for frame synchronization. at the receiver side, a pll is needed to re-generate the bit clock, translating to a higher receiver power dissipation. fss mode: the serial clock clk is truly synchronous with the serial data. embedded synchronization words are transmitted in the non-active display area for pixel synchronization. the receiver pll is powered down during this mode, hence the lower power consumption when compared wi th pss mode. the special embedded synchronization words are guaranteed by desig n to never trigger false synchronization. 7.4.3.2 pll the pll locks onto the pclk input during transmit mode or the clk input during receiver mode. it generates an internal high-speed clock, which is phase-aligne d to the input clock. the pll logic uses the lane select and transm it/receive status to determine the necessary pll bandwidth settings and pll divider values automatically. the pll is able to track spread spectrum clocking to reduce emi. the spread spectrum clock modulation frequency can be from 30 khz to 33 khz. transmitter: the internally generated clock is always aligned to the input clock pclk. ? pss mode: refer to section 7.4.1 . ? fss mode: the output clock clk is double data rate (ddr) and both clock edges are aligned to the data output. receiver: ? pss mode: the pll genera tes an internal clock at seri al bit frequency and locks to the input clock clk. ? fss mode: the receiver uses double data rate (ddr) input clock clk, which is aligned to the data already. 7.4.4 hs , vs and de signal usage in various ptn3700 modes when frame mixing is not used in pss mode, vs , hs , de, r[7:0], g[7:0], b[7:0] are treated as arbitrary user data. in this mode, ptn3700 functions as a pure serializer and deserializer, and is unaware of the meaning or polarity of vs , hs , de, r[7:0], g[7:0], b[7:0]. in fss mode, ptn3700 makes use of vs , hs and de to implement pixel synchronization with embedded sync words in the non-active display area. when frame mixing is used, vs , hs , de and r[7:0], g[7:0], b[7:0] are used to implement nxp-patented frame mixing algorithm. ta b l e 8 summarizes the requirements of vs , hs , de and rgb in various modes.
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 16 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic [1] ?x? signifies that ptn3700 handles this signal transparently, i.e., data is transmitted and received as-is. [2] ?r, g, b? signifies that r, g, b video data have to be input according to the exact chosen pin configuration of ptn3700, specifically: a) bit order reversal is not allowed, even if both the transmit data and receive data are reversed in bit order. for example, the msb of ?r? color from video source must be input as ?r7?. b) ?r? must be used for red color, ?g? for green color, and ?b? for blue color. 7.4.4.1 pss mode hs , vs and de are treated by ptn3700 in the same way as rgb signals in pss mode; that is, hs , vs , and de are serialized and transmitted transparently by the ptn3700 transmitter, and transparently received and deserialized by ptn3700 receiver. data enable (de) signal is typically used to signif y the active display area from the non-active display area. in the case that advanced frame mixing is not used: ? de signal can be tied high or low, for displays not using de signal. ? hs and vs can be active high or active low. 7.4.4.2 fss mode in fss mode, ptn3700 uses true source synchronous transmission with a serial double data rate (ddr) bit cl ock for the serial data. fss mode requires the following operating conditions: ? active low hs ? active low vs ? active high de in fss mode, de = 1 means active video, and ptn3700 generates embedded sync words when de = 0. de, vs and hs must be actively driven ac cording to the typical video screen figure shown in figure 18 . table 8. vs , hs , de, and rgb requirements [1] [2] fss mode fm vs , hs de r, g, b a[1:0] low pss high active low active high r, g, b x low x x x x high fss high active low active high r, g, b x low active low active high x x
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 17 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7.5 power modes the ptn3700 has three different power modes to minimize power consumption of the link as a function of link activity: shutdown m ode, standby mode, and active mode. the truth table for the three power modes is shown in ta b l e 9 and ta b l e 1 0 . ? shutdown mode: by driving input pin xsd low, the ptn3700 assumes lowest power mode. all internal logic circuits are reset during this mode, and the link is completely inactive. the transmitter high-speed serial output channels are put in high-impedance state, and the receiver high-speed serial input channels are pulled low. the receiver cmos parallel outputs will all be set high with the exception of de and pclk which are reset low. however, the input buffers for the transmitter remain active, so it is recommended to stop pclk and rgb data to achieve the lowest shutdown mode power. ? standby mode: when pin xsd is set high but no input clock is active, the ptn3700 detects inactivity of the clock 3 and remains in a low-power standby mode until an active input clock is detected. the transmitter serial outputs, receiver serial inputs and receiver parallel outputs all behave identically to their respective states in shutdown mode. ? active mode: when pin xsd is set high and an active input clock is detected, ptn3700 will assume normal link operation . current consumpti on depends on the pclk frequency, number of lanes, fss/pss mode, data pattern, etc. 3 numbers correspond to [de, hs , vs ] fig 18. typical video screen 002aac803 000 001 010 011 011 010 011 010 hs = 0 hs = 1 001 011 001 011 011 011 011 active video 111 vs = 0 vs = 1 3. the ptn3700 clock detection circuit identifies the clock as in active when the pclk input signal frequency is less than 500 khz . table 9. power modes - transmitter mode inputs power mode outputs xsd pclk d0+, d0 ? , d1+, d1 ? , d2+, d2 ? clk+, clk ? l x shutdown high-z high-z h stopped standby high-z high-z h running active active serial data active
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 18 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7.6 link error detection and correction in transmitter mode, ptn3700 calculates an odd parity bit and merges this into the serialized output data stream to allow the receiver to detect whether parity has been violated for its received input data. the parity bit cp is calculated across the 27-bit input data word (r[7:0], g[7:0], b[7:0], hs , vs and de) for every pixel transmitted, as shown in ta b l e 11 . note that the auxiliary bits a[1:0] are excluded from the parity calculation. in receiver mode, the received encoded parity bit cp is compared against the received 27-bit input data word (r[7:0], g[7:0], b[7:0], hs , vs and de) for every pixel, and an error is flagged by setting parity error output cpo high for the duration of the pixel clock period in which the error was detected . note that the auxiliary outp ut bits a[1:0] are excluded from the parity detection. in addition, during the pixel clock period in wh ich the error occurs, the last valid pixel word is output to r[7:0], g[7:0], b[7:0], hs , vs and de instead of the current erroneous pixel data. the last valid pixel word is defined as the data prior to the first parity error detected in any concatenation of parity errors. if a parity error is detected but no valid previous pixel information is av ailable, the receiver will output values r[7:0] = g[7:0] = b[7:0] = hs = vs = high, and de = low. the truth table for receiver parity function is shown in ta b l e 1 2 . note that the auxilia ry bits a[1:0] are not affected by the last valid pixel repetition. table 10. power modes - receiver mode inputs state of serial data inputs d0+, d0 ? , d1+, d1 ? , d2+, d2 ? power mode data outputs xsd clk+, clk ? r[7:0], g[7:0], b[7:0], hs , vs de, pclk l x or floating resistively pulled h or l shutdown h l h stopped resistively pulled h or l standby h l h running normal receiver state active active data active table 11. parity encoding function table - transmitter mode inputs encoded parity bit xsd pclk ? of inputs = h (r[7:0], g[7:0], b[7:0], hs ,vs ,de) cp h running odd l h running even h h stopped x or floating undefined l x or floating x or floating undefined
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 19 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic [1] yyy n = current valid pixel data is out put to the parallel interface. [2] yyy 0 = most recent valid pixel data is output to the parallel interface. 7.7 frame mixing and advanced frame mixing when ptn3700 is configured as receiver (tx/rx = low), the cmos input fm selects whether the frame mixing function is turned on (fm = high) or off (fm = low). (when ptn3700 is configured as transmitter (tx/rx = high), the frame mixing function is not available, and the fm input should not be used.) advanced frame mixing is a proprietary pixel mapping algorithm that features the ability to render full 24-bit color resolution (provided 24-b it source data is input) using an 18-bit or an 18-bit plus display. when frame mixing is off, th e full 24-bit data path is ma intained unaltered for the link (transparent). when frame mixing is enabled, the algorithm maps the incoming 24-bit data to the 18-bit output data, aligned to the msb. this is illustrated in ta b l e 1 3 . the new 18-bit data fields (r[7:2] fm , g[7:2] fm and b[7:2] fm ) contain the altered information as calculated by the frame mixing algorithm from the original data. one additional ?advanced frame mixing? bit is encoded into the next lower significant bit (r1 afm , g1 afm and b1 afm ) of the output data. when using frame mixing with normal 18-bit displays, the 6 msbs of the parallel video data outputs (r[7:2], g[7:2] and b[7:2]) should be connected to the display driver inputs. when using special ?18-bit plus? display drivers (advanced frame mixing capable), additionally the next lower significant bit (r1, g1 and b1) should be connected to the corresponding display driver input. table 12. parity decoding function table - receiver mode inputs received parity bit parity output data outputs xsd clock ? of bits received in frame = h (r[7:0], g[7:0], b[7:0], hs , vs , de) cp cpo r[7:0], g[7:0], b[7:0], hs , vs , de [1] [2] h running odd l l rgb n , hs n , vs n , de n h running even l h rgb 0 , hs 0 , vs 0 , de 0 h running odd h h rgb 0 , hs 0 , vs 0 , de 0 h running even h l rgb n , hs n , vs n, den h stopped x or floating x l undefined l x or floating x or floating x l undefined table 13. advanced frame mixing bit mapping (fm = high) bit 7 6 5 4 3 2 1 0 input data r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 output data r7 fm r6 fm r5 fm r4 fm r3 fm r2 fm r1 afm high g7 fm g6 fm g5 fm g4 fm g3 fm g2 fm g1 afm high b7 fm b6 fm b5 fm b4 fm b3 fm b3 fm b1 afm high
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 20 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 7.8 auxiliary signals the two auxiliary bits a[1:0] are user-supplied bits that can be addi tionally serialized and deserialized by the ptn3700 in transmitter and receiver modes, respectively. these auxiliary bits are transparent to the ptn37 00 and can be used to transmit and receive miscellaneous status or mode information across the link to the display. note that the auxiliary bits a[1:0] are excluded from the parity ca lculation and detection in the transmitter and receiver modes respectively. even in the event of parity error being detected in the receiver mode, a[1:0] will still be deserialized as they are detected by the receiver. 8. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] machine model: ansi/eos/esd-s5.2.1-1999, standard for esd sensitivity testing, machine model - component level; electrostatic disc harge association, rome, ny, usa. [3] charged device model: ansi/eos/esd-s5.3.1-1999, st andard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 9. recommended operating conditions table 14. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +3.0 v v i input voltage receiver ? 0.3 v dd + 0.5 v v o output voltage driver ? 0.3 v dd +0.5 v t stg storage temperature ? 65 +150 ? c v esd electrostatic discharge voltage hbm [1] - 1500 v mm [2] - 200 v cdm [3] - 1000 v table 15. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 1.65 1.8 1.95 v v i input voltage 0 - v dd v i oh high-level output current 0.8 ? v dd -- ? 1ma i ol low-level output current 0.2 ? v dd --1ma t amb ambient temperature oper ating in free air ? 40 - +85 ? c
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 21 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 10. static characteristics table 16. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit v dd supply voltage 1.65 1.8 1.95 v v ih high-level input voltage i i = ? 10 ? a0.7v dd -v dd v v il low-level input voltage i i =10 ? a0-0.3v dd v v oh high-level output voltage i o = ? 1 ma 0.8v dd -v dd v v ol low-level output voltage i o = 1 ma 0 - 0.2v dd v c i input capacitance tx mode - 2 4 pf transmitter mode, pss mode (tx/rx = high; fss = low) i dd supply current shutdown mode; t amb = ? 40 ? cto+60 ? c -410 ? a standby mode; t amb = ? 40 ? cto+60 ? c -410 ? a active mode [1] pclk = 6 mhz; mode 00 - 11 12.6 ma pclk = 12 mhz; mode 00 - 15 17.3 ma pclk = 20 mhz; mode 00 - 21 23.5 ma pclk = 8 mhz; mode 01 - 13 14.8 ma pclk = 22 mhz; mode 01 - 19 21.2 ma pclk = 40 mhz; mode 01 - 26 29.3 ma pclk = 20 mhz; mode 10 - 19 21.1 ma pclk = 40 mhz; mode 10 - 26 28.8 ma pclk = 65 mhz; mode 10 - 35 36.8 ma transmitter mode, fss mode (tx/rx = high; fss = high) i dd supply current shutdown mode; t amb = ? 40 ? cto+60 ? c -410 ? a standby mode; t amb = ? 40 ? cto+60 ? c -410 ? a active mode [1] pclk = 6 mhz; mode 00 - 12 13.7 ma pclk = 12 mhz; mode 00 - 17 19.2 ma pclk = 20 mhz; mode 00 - 24 26.6 ma pclk = 8 mhz; mode 01 - 13 14.9 ma pclk = 22 mhz; mode 01 - 20 22.3 ma pclk = 40 mhz; mode 01 - 28 31.9 ma pclk = 20 mhz; mode 10 - 19 21.2 ma pclk = 40 mhz; mode 10 - 26 29.1 ma pclk = 65 mhz; mode 10 - 35 38.9 ma
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 22 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic [1] worst-case data pattern for power dissipa tion is used: alternating vertical stripes . the colors of the stripes correspond to the data pattern: rgb[23:0] = 0xaa aaaa (odd stri pes) / rgb[23:0] = 0x55 5555 (even stripes). [2] based on receiver output load (per output) of 16 pf. the loaded outputs are: pclk, r[7:0], g[7:0], b[7:0], hs , vs and de. receiver mode, pss mode (tx/rx = low; fss = low) [2] i dd supply current shutdown mode; t amb = ? 40 ? cto+60 ? c -410 ? a standby mode; t amb = ? 40 ? cto+60 ? c -410 ? a active mode [1] pclk = 6 mhz; mode 00 - 8 10.7 ma pclk = 12 mhz; mode 00 - 14 16.5 ma pclk = 20 mhz; mode 00 - 22 25 ma pclk = 8 mhz; mode 01 - 8.5 11 ma pclk = 22 mhz; mode 01 - 16 19.5 ma pclk = 40 mhz; mode 01 - 25 31 ma pclk = 20 mhz; mode 10 - 14 17.8 ma pclk = 40 mhz; mode 10 - 22.5 28 ma pclk = 65 mhz; mode 10 - 34 40 ma receiver mode, fss mode (tx/rx = low; fss = high) [2] i dd supply current shutdown mode; t amb = ? 40 ? cto+60 ? c -410 ? a standby mode; t amb = ? 40 ? cto+60 ? c -410 ? a active mode [1] pclk = 6 mhz; mode 00 - 7.5 10.2 ma pclk = 12 mhz; mode 00 - 13 15.5 ma pclk = 20 mhz; mode 00 - 20.6 23.6 ma pclk = 8 mhz; mode 01 - 8.1 10.6 ma pclk = 22 mhz; mode 01 - 15.4 18.6 ma pclk = 40 mhz; mode 01 - 23.4 29.3 ma pclk = 20 mhz; mode 10 - 13.5 17.3 ma pclk = 40 mhz; mode 10 - 21.8 26.9 ma pclk = 65 mhz; mode 10 - 33 38 ma table 16. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 23 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 11. dynamic characteristics 11.1 transmitter mode table 17. dynamic characteristics for transmitter mode v dd = 1.65 v to 1.95 v, t amb = ? 40 ? c to +85 ? c, unless otherwise specified. all cmos input signals? rise time and fall time to transmitter are stipulated to be from 1 ns to 15 ns. symbol parameter conditions min typ max unit f i(pclk) input frequency on pin pclk mode 00; see table 5 4.0 - 21.6 mhz mode 01; see table 5 8.0 - 43.3 mhz mode 10; see table 5 20.0 - 65.0 mhz ? i(pclk) input duty cycle on pin pclk 33 - 67 % t pclk t su(d-pclk) set-up time from data input to pclk 2.0--ns t h(d-pclk) hold time from data input to pclk 2.0--ns t jit(cc) cycle-to-cycle jitter time pclk ? 300 - +300 ps b pll(loop) pll loop bandwidth ? 3 db corner frequency of pll loop filter response 0.02 ? f i(pclk) 0.03 ? f i(pclk) 0.05 ? f i(pclk) mhz fig 19. ac timing diag ram - transmitter mode 002aab367 0.7v dd 0.3v dd 0.7v dd 0.3v dd pclk vs, hs, de, r[7:0], g[7:0], b[7:0] t su(d-pclk) t h(d-pclk)
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 24 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 11.2 receiver mode table 18. dynamic characteristics for receiver mode v dd = 1.65 v to 1.95 v, t amb = ? 40 ? c to +85 ? c, unless otherwise specified. cmos output load c l =16pf. symbol parameter conditions min typ max unit f o(pclk) output frequency on pin pclk mode 00; see table 5 4.0 - 21.6 mhz mode 01; see table 5 8.0 - 43.3 mhz mode 10; see table 5 20.0 - 65.0 mhz ? o(pclk) output duty cycle on pin pclk mode 00 or mode 10; f/xs =1 45 50 55 % t pclk mode 01; f/xs = 1 48 53 59 % t pclk t sk(q) data output skew time mode 00; f/xs =1 ? 0.5 0 1.5 ns mode 01; f/xs =1 ? 0.5 0 0.8 ns mode 10; f/xs =1 ? 0.5 0 0.8 ns mode 00; f/xs =0 ? 3.0 0 2.0 ns mode 01; f/xs =0 ? 0.5 0 2.5 ns mode 10; f/xs =0 ? 1.4 0 3.0 ns t jit(r)pclk pclk rise jitter time ? 0.6 0 0.6 ns t r rise time cmos signals mode 00; f/xs = 0 8 - 18 ns mode 00; f/xs = 1 4 - 10 ns mode 01; f/xs = 0 4 - 10 ns mode 01; f/xs =11- 3ns mode 10; f/xs = 0 4 - 10 ns mode 10; f/xs =11- 3ns t f fall time cmos signals mode 00; f/xs = 0 8 - 18 ns mode 00; f/xs = 1 4 - 10 ns mode 01; f/xs = 0 4 - 10 ns mode 01; f/xs =11- 3ns mode 10; f/xs = 0 4 - 10 ns mode 10; f/xs =11- 3ns b pll(loop) pll loop bandwidth ? 3 db corner frequency of pll loop filter response 0.09 ? f o(pclk) 0.11 ? f o(pclk) 0.14 ? f o(pclk) mhz
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 25 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic fig 20. ac timing diagram - receiver mode t jit(r)pclk 002aab368 t sk(q) 0.8v dd 0.2v dd 0.8v dd 0.2v dd pclk vs, hs, de, r[7:0], g[7:0], b[7:0]
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 26 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 11.3 power-on/power-off sequence 11.3.1 power-on sequence table 19. power-on sequence timing characteristics v dd = 1.65 v to 1.95 v, t amb = ? 40 ? c to +85 ? c, unless otherwise specified. these values are for transitions of t he shutdown mode to the standby mode and the standby mode to the active mode. symbol parameter conditions min typ max unit t su(vddh-xsdh) set-up time from v dd high to xsd high transmitter mode 0 - - ms receiver mode 0 - - ms t su(xsdh-pclkv) set-up time from xsd high to pclk valid transmitter mode 10 - - ? s t d(pclkh-dv) delay time from pclk high to data valid transmitter mode - - 2 ms t d(xsdh-stb) delay time from xsd high to standby receiver mode - - 10 ? s t d(rxdv-rxqv) delay time from receiver data input valid to receiver data output valid receiver mode - - 2 ms fig 21. power-on sequence of the link v dd transmitter mode xsd 0.7v dd pclk stopped provided high-z valid outputs reflecting high-speed channels shutdown standby defined in the shutdown or standby mode high-speed signal outputs v dd xsd power mode all data outputs and pclk valid receiver mode t su(vddh-xsdh) t su(xsdh-pclkv) t d(pclkh-dv) t su(vddh-xsdh) t d(xsdh-stb) t d(rxdv-rxqv) high-z high-speed signal inputs valid 002aab369
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 27 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 11.3.2 power-off sequence table 20. power-off sequence timing characteristics v dd = 1.65 v to 1.95 v, t amb = ? 40 ? c to +85 ? c, unless otherwise specified. these values are for transition of the active mode to the standby mode. symbol parameter conditions min typ max unit t d(pclkl-txqz) delay time from pclk low to transmitter data output float transmitter mode - - 100 ? s t d(rxdz-rxqinact) receiver data input float to receiver data output inactive delay time receiver mode - - 5 ? s t h(xsdl-vddl) supply voltage low after xsd low hold time transmitter mode 0 - - ms receiver mode 0 - - ms fig 22. power-off sequence of the link receiver mode xsd transmitter mode pclk provided stopped high-impedance valid 002aab370 transmitter mode high-speed signal outputs t d(pclkl-txqz) t h(xsdl-vddl) t h(xsdl-vddl) transmitter mode v dd receiver mode v dd high-impedance valid valid outputs reflecting high-speed channels defined in the shutdown mode or standby mode receiver mode high-speed signal inputs t d(rxdz-rxqinact) receiver mode all outputs r[7:0], g[7:0], b[7:0], vs, hs de, pclk transmitter mode xsd 0.3v dd 0.3v dd
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 28 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 11.4 high-speed signaling channel [1] [2] mode 00: ui = pclk period / 30 mode 01: ui = pclk period / 15 mode 10: ui = pclk period / 10 [3] n is defined as the bit position, where 0 ? n ? 29 (mode 00), 0 ? n ? 14 (mode 01) or 0 ? n ? 9 (mode 10). table 21. high-speed signaling channel sublvd s output characteristics, transmitter mode v dd = 1.65 v to 1.95 v, t amb = ? 40 ? c to +85 ? c, unless otherwise specified. see section 13.1 for testing information. symbol parameter conditions min typ max unit v o(dif) differential output voltage see figure 28 100 150 200 mv v o(cm) common-mode output voltage see figure 28 0.8 0.9 1.0 v v o(cm)ripple(p-p) peak-to-peak ripple common-mode output voltage see figure 29 ? 75 - +75 mv r o(dif) differential output resistance between complimentary outputs of any differential pair: clk+/clk ? ; d0+/d0 ? ; d1+/d1 ? ; d2+/d2 ? 80 180 280 ? t r(dif) differential rise time from 20 % to 80 % of v o(dif) ; see figure 30 200 - 500 ps t f(dif) differential fall time from 80 % to 20 % of v o(dif) ; see figure 30 200 - 500 ps f oper operating frequency - - 325 mhz i o output current output drive current per channel - - 4 ma ? v o(dif) /v o(dif) relative differential output voltage difference between clk+/clk ? and dn+/dn ? , referenced to clk+/clk ? [1] ? 10 - +10 % ? v o(cm) common-mode output voltage difference between clk+/clk ? and dn+/dn ? ? 0.1 - +0.1 v ? t r rise time difference t r (clk+/clk ? ) ? t r (dn+/dn ? ) ? 100 - +100 ps ? t f fall time difference t f (clk+/clk ? ) ? t f (dn+/dn ? ) ? 100 - +100 ps i lo output leakage current shutdown or standby mode (high-impedance state) ? 3.0 - +3.0 ? a t bit(clkh-q) bit time from clk high to data output pss mode; mode 00 or mode 01; see ta b l e 5 , figure 33 [2] [3] n ? ui ? 19 % ? ui n ? ui n ? ui +19% ? ui ps pss mode: mode 10; see ta b l e 5 , figure 33 [2] [3] n ? ui ? 16 % ? ui n ? ui n ? ui +16% ? ui ps t sk(clk-q) clk edge to data output skew time fss mode; see figure 35 [2] ? 16 % ? ui 0 +16 % ? ui ps ? % ?? v odif ?? clk v odif ?? data ? v odif ?? clk -------------------------------------------------------------- - 100 % ? =
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 29 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic [1] [2] mode 00: ui = pclk period / 30 mode 01: ui = pclk period / 15 mode 10: ui = pclk period / 10 [3] n is defined as the bit position, where 0 ? n ? 29 (mode 00), 0 ? n ? 14 (mode 01) or 0 ? n ? 9 (mode 10). table 22. high-speed signaling channel sublvds input characteristics, receiver mode v dd = 1.65 v to 1.95 v, t amb = ? 40 ? c to +85 ? c, unless otherwise specified. see section 13.1 for testing information. symbol parameter conditions min typ max unit v i(dif) differential input voltage see figure 31 70 100 200 mv v th(h)i(dif) differential input high-level threshold voltage see figure 32 +25 - - mv v th(l)i(dif) differential input low-level threshold voltage see figure 32 -- ? 25 mv v i(cm) common-mode input voltage see figure 31 0.4 - 1.4 v v i(cm)ripple(p-p) peak-to-peak ripple common-mode input voltage see figure 29 ? 75 - +75 mv r i(dif) differential input resistance internal termination resistor; see figure 31 80 100 120 ? t r(dif) differential rise time from 20 % to 80 % of v i(dif) ; see figure 30 --800ps t f(dif) differential fall time from 80 % to 20 % of v i(dif) ; see figure 30 --800ps f oper operating frequency - - 325 mhz ? v i(dif) /v i(dif) relative differential input voltage difference between clk+/clk ? and dn+/dn ? , referenced to clk+/clk ? [1] ? 10 - +10 % ? v i(cm) common-mode input voltage difference between clk+/clk ? and dn+/dn ? ? 0.1 - +0.1 v ? t r rise time difference t r (clk+/clk ? ) ? t r (dn+/dn ? ) ? 100 - +100 ps ? t f fall time difference t f (clk+/clk ? ) ? t f (dn+/dn ? ) ? 100 - +100 ps r pd pull-down resistance complimentary input (dn ? ) to gnd; input clock inactive; see figure 31 -150k ? i li input leakage current shutdown or standby mode ? 90 - +90 ? a t bit(clkh-d) bit time from clk high to data input pss mode; see figure 34 [2] [3] n ? ui ? 21 % ? ui n ? ui n ? ui +21% ? ui ps t sk(clk-d) clk edge to data input skew time fss mode; see figure 35 [2] ? 21 % ui 0 +21 % ui ps ? % ?? v idif ?? clk v idif ?? data ? v idif ?? clk ----------------------------------------------------------- 100 % ? =
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 30 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 12. application information 12.1 typical lane and pclk configurations the ptn3700 supports pclk (pixel clock) frequencies from 4 mhz to 65 mhz over 1, 2 or 3 data lanes. ta b l e 2 3 shows the typical number of data lanes needed, assuming blanking overhead of 20 %. note that 20 % overhead is an exampl e value for illustration/calculation purposes only and not a requirement. 12.2 pin configurations for various topologies of pcb there are two input pins, psel1 and psel0, on the ptn3700 that allow for pinning order configurations. psel1 will change the pinning order of the serial signals, and allow for various topologies of pcb or flex layout without crossing the high-speed differential traces. the example shown in figure 23 has set psel1 = 0 at receiver side, and psel1 = 1 at the transmitter to avoid the traces crossing. figure 24 shows another configur ation, which has psel1 = 1 at receiver, and psel1 = 0 at transmitter. psel0 can configure the pinning order of the parallel sign als, and enables the easy introduction of the ptn3700 into an existing parallel design avoiding board re-layout. figure 23 and figure 24 show two configuration examples. table 23. typical pclk and number of data lanes panel horizontal vertical color bit other bits frame rate (hz) blanking overhead pixel clock (mhz) serial aggregate data rate (mbit/s) 1-lane 2-lane 3-lane qvga 240 320 18 12 60 20 % 5.5 165.9 wqvga 400 240 18 12 60 20 % 6.9 207.4 cif+ 352 416 18 12 60 20 % 10.5 316.3 316.3 hvga 320 480 24 6 60 20 % 11.1 331.8 331.8 vga 640 480 24 6 60 20 % 22.1 663.6 663.6 wvga 854 480 24 6 60 20 % 29.5 885.4 885.4 svga 800 600 24 6 60 20 % 34.6 1036.8 1036.8 xga 1024 768 24 6 60 20 % 56.6 1698.7 720p 1280 720 24 6 60 15 % 63.6 1909.7
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 31 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic transparent top view. fig 23. pinning configuration example 1 d0 ? vdda de hs b0 b2 d0+ gnda vs pclk b1 b3 clk ? tx/rx a1 gnd vdd b6 clk+ psel0 ls0 fm g0 d1 ? gnd psel1 ls1 fss g2 d1+ f/xs gnd vdd g4 vdd a0 b4 b5 b7 g1 g3 g5 d2 ? xsd r6 r4 r2 r0 d2+ cpo r5 r3 r1 r7 g6 g7 002aac935 ball a1 index transmitter mode psel1 = 1 psel0 = 0 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 pclk hs vs de d2+ vdda r7 r5 r3 r1 d2 ? gnda r6 r4 r2 r0 d1+ tx/rx a1 gnd vdd g5 d1 ? psel0 ls0 fm g3 clk+ gnd psel1 ls1 fss g1 clk ? f/xs gnd vdd b7 vdd a0 g7 g6 g4 g2 g0 b6 d0+ xsd pclk b1 b3 d0 ? cpo b0 b2 de b5 b4 vs hs ball a1 index r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b5 b4 b3 b2 b1 b0 pclk hs vs de receiver mode psel1 = 0 psel0 = 0 b6 transparent top view. fig 24. pinning configuration example 2 d2+ vdda de hs r7 r5 d2 ? gnda vs pclk r6 r4 d1+ tx/rx a1 gnd vdd r1 d1 ? psel0 ls0 fm g7 clk+ gnd psel1 ls1 fss g5 clk ? f/xs gnd vdd g3 vdd a0 r3 r2 r0 g6 g4 g2 d0+ xsd b1 b3 b5 b7 d0 ? cpo b2 b4 b6 b0 g1 g0 002aac936 ball a1 index transmitter mode psel1 = 0 psel0 = 1 b0 b1 b2 b3 b4 b5 b6 b7 g0 g1 g2 g3 g4 g5 g6 g7 r0 r1 r2 r3 r4 r5 r6 r7 pclk hs vs de d0 ? vdda b0 b2 b4 b6 d0+ gnda b1 b3 b5 b7 clk ? tx/rx a1 gnd vdd g2 clk+ psel0 ls0 fm g4 d1 ? gnd psel1 ls1 fss g6 d1+ f/xs gnd vdd r0 vdd a0 g0 g1 g3 g5 g7 r1 d2 ? xsd pclk r6 r4 d2+ cpo r7 r5 de r2 r3 vs hs ball a1 index b0 b1 b2 b3 b4 b5 b6 b7 g0 g1 g2 g3 g4 g5 g6 g7 r0 r2 r3 r4 r5 r6 r7 pclk hs vs de receiver mode psel1 = 1 psel0 = 1 r1
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 32 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 12.3 power decoupling configuration the ptn3700 needs 1.8 v v dd and 1.8 v v dda . both can share the same voltage regulator, and use a 10 ? resistor for isolation. the recommended power configuration of the decoupling is shown in figure 25 . it is recommended to install one 0.1 ? f ceramic capacitor for each vdd pin and one 0.01 ? f ceramic capacitor for v dda pin, and the lead length between the ic power pins and deco upling capacitors should be as short as possible. 12.4 pcb/flex layout guideline the high data rate at the serial i/o requires some specific implementations in the pcb and flex layout design. the following practices can be used as guideline: ? the differential pair must be routed symmetrically. keep all four pairs of differential signal traces the same length. the difference in trace length should be less than 20 mils. ? maintain 100 ? differential impedance. ? do not route signals over any plane split; use only one ground plane underneath the differential signals. ? avoid any discontinuity for signal integrity. differential pairs should be routed on the same layer and the number of vias on the differential traces should be minimized. test points should be placed in series and symmetrically. stubs should not be introduced on the differential pairs. 12.5 power-on/power-off requirement ptn3700 does not have any external reset pin. internally, there is power-on reset (por) circuitry to reset the whole ic at power-up. in order to guarantee that por works properly, the supply voltage v dd must be powered up from gr ound level, as illustrated in figure 26 . fig 25. power decoupling configuration vdd 0.1 f 0.1 f 0.1 f 10 0.01 f vdda 002aac937 fig 26. expected and unexpected power-on behavior 002aag311 expected behavior. power-up from gnd level enables ptn3700 to start up correctly with stable por. unexpected behavior. power-up from a higher than gnd level might set ptn3700 to an unstable state without proper por. v dd gnd
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 33 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic it is recommended to have long en ough of a power-off time to let v dd discharge completely, reaching to ground level. if the supply voltage v dd cannot be guaranteed to start from ground level, it is recommended to hold the xsd pin at low during power-on. 13. test information 13.1 high-speed signaling channel measurements fig 27. xsd at low during power-on 002aag312 v dd gnd gnd xsd fig 28. transmitter termination and definition for measurement of electrical parameters fig 29. voltage waveforms, common mode ripple measurement (single-ended mode) 49.9 1 % 49.9 1 % + ? clk, d0, d1 or d2 v o(cm) v o(dif) 002aac101 v i(cm) , v o(cm) dn+, clk+ dn ? , clk ? v i(cm)ripple(p-p) , v o(cm)ripple(p-p) 002aac102
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 34 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic fig 30. voltage waveforms, differential input or output voltage and rise and fall time measurements fig 31. receiver measurement definition fo r measurement of electrical parameters fig 32. voltage waveforms, input threshold voltage measurements fig 33. transmitter high-spee d serial outputs timing relationships (pss mode) v i(dif) , v o(dif) 002aac103 0 v t r(dif) t f(dif) 60 % 20 % 20 % v i(dif) 002aac104 r i(dif) receiver v i(cm) r pd v th(h)i(dif) 002aac105 0 v differential (dn+ ? dn ? ), (clk+ ? clk ? ) v th(l)i(dif) 0 v d0, d1 or d2 (differential) 002aac106 0 v clk (differential) t bit(clkh-q) bit 0 t bit(clkh-q) bit 1 t bit(clkh-q) bit n bit 0 bit 1 bit n
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 35 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic fig 34. receiver high-speed serial inputs timing relationships (pss mode) fig 35. transmitter and receiver high-speed serial outputs and inputs timing relationships (fss mode) 0 v d0, d1 or d2 (differential) 002aac806 0 v clk (differential) t bit(clkh-d) bit 0 t bit(clkh-d) bit 1 t bit(clkh-d) bit n bit 0 bit 1 bit n 0 v d0, d1 or d2 (differential) 002aac807 0 v clk (differential) t sk(clk-q) , t sk(clk-d) t sk(clk-q) , t sk(clk-d)
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 36 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 14. package outline fig 36. package outline sot991-1 (vfbga56) references outline version european projection issue date iec jedec jeita sot991-1 - - - - - - - - - sot991-1 07-02-06 07-02-07 unit a max mm 1 0.25 0.15 0.75 0.60 4.1 3.9 4.6 4.4 0.5 3 0.15 0.05 0.1 a 1 dimensions (mm are the original dimensions) vfbga56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 x 4.5 x 0.65 mm 0 2.5 5 mm scale a 2 b 0.35 0.25 d e e e 1 e 2 3.5 v w y 0.08 y 1 c y c y 1 x b e 2 e 1 e e 1/2 e a c b ? v m c ? w m a b c d e f h g 246 1357 ball a1 index area b a ball a1 index area e d detail x a a 1 a 2
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 37 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 15. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 15.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 38 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 15.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 37 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 4 and 25 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 37 . table 24. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ? c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 25. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ? c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 39 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 16. abbreviations msl: moisture sensitivity level fig 37. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 26. abbreviations acronym description cif common intermediate format cmos complementary metal oxide semiconductor ddr double data rate emi electromagnet ic interference fps frames per second hvga half-size video graphics array i/o input/output lvds low-voltage differential signalling msb most significant bit pcb printed-circuit board pll phase-locked loop qvga quarter video graphics array rgb red/green/blue smili simple mobile interface link sublvds sub low-voltage differential signalling svga super video graphics array ui unit interval vga video graphics array wqvga wide quarter video graphics array
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 40 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 17. revision history wvga wide video graphics array xga extended graphics array xvga extended video graphics array table 26. abbreviations ?continued acronym description table 27. revision history document id release date data sheet status change notice supersedes ptn3700 v.2 20110608 product data sheet - ptn3700 v.1 modifications: ? added section 12.5 ? power-on/power-off requirement ? ? updated soldering information ptn3700 v.1 20070814 product data sheet - -
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 41 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
ptn3700 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 june 2011 42 of 43 nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors ptn3700 1.8 v simple mobile interface link bridge ic ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 june 2011 document identifier: ptn3700 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . . 9 7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 link programmability . . . . . . . . . . . . . . . . . . . 10 7.3 versatile signal mirroring programmability . . . 10 7.4 high-speed data channel protocol options . . . 12 7.4.1 serial protocol bit mapping - pseudo source synchronous mode (fss = low). . . . . . . . . . 13 7.4.2 serial protocol bi t mapping - fully source synchronous mode (fss = high) . . . . . . . . . 14 7.4.3 pll, pclk, clk and pixel synchronization . . 15 7.4.3.1 pixel synchronization . . . . . . . . . . . . . . . . . . . 15 7.4.3.2 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4.4 hs , vs and de signal usage in various ptn3700 modes. . . . . . . . . . . . . . . . . . . . . . . 15 7.4.4.1 pss mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4.4.2 fss mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5 power modes . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 link error detection and correction . . . . . . . . . 18 7.7 frame mixing and advanced frame mixing . . 19 7.8 auxiliary signals . . . . . . . . . . . . . . . . . . . . . . . 20 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20 9 recommended operating conditions. . . . . . . 20 10 static characteristics. . . . . . . . . . . . . . . . . . . . 21 11 dynamic characteristics . . . . . . . . . . . . . . . . . 23 11.1 transmitter mode . . . . . . . . . . . . . . . . . . . . . . 23 11.2 receiver mode . . . . . . . . . . . . . . . . . . . . . . . . 24 11.3 power-on/power-off sequence . . . . . . . . . . . . 26 11.3.1 power-on sequence . . . . . . . . . . . . . . . . . . . . 26 11.3.2 power-off sequence . . . . . . . . . . . . . . . . . . . . 27 11.4 high-speed signaling channel . . . . . . . . . . . . 28 12 application information. . . . . . . . . . . . . . . . . . 30 12.1 typical lane and pclk configurations . . . . . . 30 12.2 pin configurations for various topologies of pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.3 power decoupling configuration . . . . . . . . . . . 32 12.4 pcb/flex layout guideline . . . . . . . . . . . . . . . 32 12.5 power-on/power-off requirement . . . . . . . . . . 32 13 test information . . . . . . . . . . . . . . . . . . . . . . . 33 13.1 high-speed signaling channel measurements . . . . . . . . . . . . . . . . . . . . . . . . 33 14 package outline. . . . . . . . . . . . . . . . . . . . . . . . 36 15 soldering of smd packages . . . . . . . . . . . . . . 37 15.1 introduction to soldering. . . . . . . . . . . . . . . . . 37 15.2 wave and reflow soldering. . . . . . . . . . . . . . . 37 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 37 15.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 38 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 40 18 legal information . . . . . . . . . . . . . . . . . . . . . . 41 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 19 contact information . . . . . . . . . . . . . . . . . . . . 42 20 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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